1. Field of the Invention
The present invention relates to a memory bank switching apparatus and, more particularly, to an apparatus for use in selection of a desired one of memory banks consisting of read-only memories (ROM) where mutually different programs are stored.
2. Description of the Prior Art
The total number of data storable in a main memory unit is determined by the number of bits of address signals. For example, when each address signal is composed of 14 bits in a case where data are accessed per byte (8 bits) thereof by individually different address signals, a total of 2.sup.14 (approx. 16,000) bytes are stored in the main memory unit and any desired byte can be accessed. In a main memory unit so constituted that 12,000 bytes out of its storage capacity of 16,000 bytes are allocated to three RAM memory banks each having a 4,000-byte storage capacity while the remaining 4,000 bytes are allocated to one ROM memory bank having a 4,000 byte storage capacity, then it becomes possible to access a desired byte in the main memory unit by a 14-bit address signal.
However, in the example mentioned above, there may arise an instance where two ROM banks each having a 4,000-byte storage capacity need to be additionally provided in view of programs to be stored in the ROMs. In such a case, it is impossible, by a 14-bit address signal alone, to access desired data out of a total of 24,000 bytes in the RAMs and ROMs. And therefore a memory bank switching apparatus is required for selectively using merely one of the three ROM memory banks.
In the conventional method of switching memory banks, it has been customary to control a switching apparatus by the application of a signal which is used for switching input/output (I/O) units connected to a computer system. Normally the computer system is equipped with a plurality of I/O units for which channel addresses are predetermined respectively. And when connection to a desired I/O unit is requested from a central processing unit (CPU), a signal of the channel address relative to such I/O unit is transmitted to connect the same to an address bus and a data bus. In the prior art, the operation of switching the memory banks has been performed heretofore in a manner similar to the above.
According to such conventional method, it is necessary to first output from the CPU a signal to discriminate between a channel address signal for selecting a desired I/O unit and a signal for specifying a desired memory bank, and then to output a data address signal. Thus, the signals to be outputted from the CPU for switching the memory banks become great in number, and there exists another unavoidable disadvantage that the hardware configuration of the switching apparatus is rendered considerably complicated to eventually bring about an increase of the production cost.